In semiconductor fabrication, a wafer typically undergoes numerous processes to form an integrated circuit. Various wafer-level tests are performed to determine performance and reliability of the integrated circuit under various conditions and wafer acceptance testing. Wafer-level reliability testing is utilized for detecting early life failure associated with defects generated during fabrication of the integrated circuit. Generally, reliability testing involves stressing the integrated circuit by various techniques such as power cycling on/off and applying voltages that exceed normal operating conditions. However, current testing techniques may provide invalid reliability assessment due to unexpected damage or degradation of the integrated circuit during testing. For example, parasitic inductance and capacitance of the test setup (e.g., probe package) may induce high damping voltage coupling to radio frequency (RF) components (e.g., LC tank circuit) of the integrated circuit which can cause unexpected damage to the integrated circuit.